1. Field of the Invention
The invention relates to a clock synthesizer, and more particularly, to a de-skew multiplier clock synthesizer with the clock divider outside the feedback loop of a PLL and a method for generating an in-phase clock utilizing the clock synthesizer.
2. Description of the Prior Art
In data transmission systems, the transmitter and the receiver must be synchronized to accurately access transmitted data. Phase locked loop (PLL) circuits have been used for many years to achieve such synchronization. A typical PLL circuit receives an accurate reference input signal and performs a feedback control operation to lock the output signal in phase with the incoming reference signal. Essentially, an analog PLL circuit continuously tests the output of a voltage-controlled oscillator (VCO) through a feedback loop, and when the output of the VCO drifts away from the incoming reference signal, an error voltage is generated to pull the VCO back into synchronization with the incoming reference signal. PLL circuits thus have been widely used in a variety of applications such as communication systems, computers networks, television transmissions, etc.
Please refer to FIG. 1. FIG. 1 shows a clock synthesizer according to the prior art. The clock synthesizer includes a PLL 18 and a clock divider 16. The PLL 18 includes three main components: a phase detector (PD) 14, a loop filter 12, and a voltage controlled oscillator (VCO) 10. The clock divider 16 adjusts the frequency of the VCO 10 output signal fout to correspond to the frequency of an incoming reference signal. The PD 14 compares an incoming reference signal fref and the fed-back output of VCO 10 fout/N, and generates an error signal which represents any phase differences between the reference signal fref and the VCO 10 output. The loop filter 12 acts as a low-pass filter, thereby removing alternating current (ac) components to provide a direct-current (dc) voltage signal to drive the VCO 10. This input voltage supplied from the loop filter 12 controls the output frequency of the VCO 10. The output fout of the VCO 10 is fed-back to the PD 14 through the clock divider 16 and is continuously driven in a direction that will minimize the error signal generated by the PD 14. Once the signals fref and fout/N are made equal, the output of VCO 10 is said to be locked to the input reference signal, and any phase differences between the two signals will be controlled.
The most important characteristic of the clock synthesizer according to the prior art should be that the clock divider must be in the feedback loop of the PLL, and it's benefit to physically simple, straightforward and low cost. However, let the clock divider be used inside the PLL feedback loop so that the initiation of the clock divider should be nothing about the de-skew requirement since the PLL would carry out the de-skew mechanism due to the physical attribute of the PLL. So there is potential PLL malfunction due to the VOC performance without the detail of the clock divider outside the PLL. The difficulty for the simulation and verification is another problem since the feedback loop is improper and hard to be simulated and verified. The design of de-skew multiplier clock synthesizers with the clock divider in the feedback loop should be hard to be maintained and migrated, and need more effort to go through the details.